first
i cant be bothered too change R9
it should be 1k too gnd
sry about that
corrects the problem at ttl level and 12 volts cmos level
the switches are just too test the bias level was ok
100k too gnd and 10 K buffer zone
the 100K are put there becouse cmos has very sensative gates
so you need too attenuate anyvoltages that will give a miss trip
the diodes use 1n4148
there is no simple solution too a latch
the rest of the switches can go although you need to replace sw1 with a 1K res too use the not enable latch so it still carries the signal for 3 but dosnt latch
or a 1k if you dont want too use this feature or to give you a no latch input by toggle the line low too disable the latch
SW2 can be removed safely
with the enable pin realy is a not disable so when its pulled low the output is turned off or low these are extra feature too what you asked but no matter handy to know
if you download proteus lite
w*w.labcenter.co.uk/download/prolite.exe
you can view it
this design is realy only half of one chip 7 diodes although you can do without d8 and 6 resistors
although you can do a similar job with a flip flop
or a schmit
this is a nicer set up as it is very flexable too also add other outcomes via just adding a two input and gate type or an or or nor gate
the 74hct4073 is a good choice for TTL levels as it comes in three voltage ranges
the design above wont need altered and will do for any 4073 varient
and still give correct output
too control other logic
quality not componet count makes for reliability {philips moto use too be}