in my specification it is working fine in static comparator, i think if i go for dynamic comparator in lay out it will be very much strenous to match the clock path, and it will burden me load thats why i am trying to avoid dynamic one.thank you.
Hi,
It may be like this....dynamic comps need more carefull attention towards sync. and clocking.....as in pipelined (standard 1.5 bit per stage) ADC....before and after S/H are there....a static comp is good enough to perform the operation without the overheads...but it is also true that dynamic comps are more efficient from speed point of view.....its ultimately a trade-off and fact of meeting the spec......
Again I will be highly obliged if u please mention some papers on the topic. I gone thru IEEE. Its not enough. Papers from other source is also appreciated.