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Any advice on hierarchical layout to avoid DRC violations on top level?

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scscsc

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Hi everyone,

when we do a chip layout, usually we do it in a hierarchy way. It means that we do the modules and blocks layout first, then the top layout. But when we do the top layout, the only physical information we have about the sub-modules and blocks is contained in the LEF files, which only give limited metal layers information about pins, power stripes, etc. And during the top layout, the automatic placement of cells may introduce some DRC violations like NW/PW minimum space without noticing it. So how do we avoid DRC violations during the hierarchical layout? Is there some common rules and tricks? Thanks
 

verymiss

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add some routing blockages to the sub-modules and some placement blockages(halo) to the boundary of blocks
 

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