If you use an AND gate to gate a clock signal, you have to ensure that the enable signal changes only during the period when the clock signal is low. If enable changes during high clock period, you will get a clipped clock pulse. You can verify by drawing waveforms. If enable signal launches from a positive edge-triggered flip-flop, we get a half cycle hold check which cannot be met in real scenario. So, if you are using AND gate, you have to ensure enable launches from negative edge flop.