Analysis of code: issue with assigning COUNT

[mmurali]

Analysis of code

I got this code from a fellow designer.

process (CLK, RES_N)
begin

if RES_N = '0' then

COUNT <= "00000000";
SOP_INT <= '0';
EOP_INT <= '0';

elsif rising_edge(CLK) then
if ENABLE = '1' then
COUNT <= COUNT + 1;
if SYNC_SIG = '1' then
COUNT <= "00000000";
SOP_INT <= '0';
EOP_INT <= '0';
elsif START_SIG = '1' then
COUNT <= "00000001";
SOP_INT <= '1';
EOP_INT <= '0';
elsif COUNT >= "11111110" then
SOP_INT <= '0';
EOP_INT <= '1';
else
SOP_INT <= '0';
EOP_INT <= '0';
end if;
end if;
end if;

If you notice he's assigned COUNT outside of the lower if condition instead of doing it within the 'else' condition. Is this code ok? I'm a bit concerned as to how the synthesis tool will interpret this code. If start_sig = '1' then COUNT will have two logic paths. In VHDL does the if statement behave like a case statement where there is default statement on top.
Thanks.

 

[nand_gates]

Re: Analysis of code

The code looks OK!
Yes here also if statement behave like a case statement where there is default statement on top.