Analysis of Battery Charger Design

[Hicham M]

Hello everyone,

I have this battery charger/power supply design and i'm trying to understand how it works
I'm stuck in the Mosfet Q1 gate driver, not sure about th purpose of the of D4 and D1

What I understood is :
when primary power supply is on ("IN_+24V" = 24V) : the Q1 gate will be 5V and V_ds = V_bat - something (positive node of D5) !!.

when primary power supply is off ("IN_+24V" = 0V) : the Q1 gate will be 0V and V_ds = 0, and the 3V7 output will be equal to 0 aswell as the 3V3 and 1V8 are all off?

Yet the battery is suppose to provide the necessary voltage when the primary power source is off,
My question is how does this happen in this circuits ??

I also have this feedback about the design that uses the +3V7 pad :
" during transmission bursts can be 2A so the voltage drop on D4 + D6 will be > 2.2V, in this case the value of VBATT could goes below 3V and the module will turn off or freeze" how did he figure out that drope of voltage ??

 

[poorchava]

Hi,

with voltage drop it's easy: the 3.7V supply is derived from 5V supply by dropping voltage across 2 diodes. Typical silicon diode such as those used in the circuit have drop of about 0.65V, so you get 3.7V. But if you look at the I-V characteristic in the datasheet of LL4007 you will see that at current of 2A the drop os almost 1.1V, so altogether you will get 2.2V of drop.

With mosfet the things are a bit tricky. The gate is typically at 5V and the source at 3.7 so Vgs is positive and mosfet is off. When the 5V rail falls below 3.7V the mosfet will start turning on it will connect 3.7V rail to battery effectively powering the 3.7V rail from it. Obviously, the mosfet will conduct from drain to source which is rather "non conventional" direction for a p-mos. It provides a low resistance path through the channel, but doesn't have any blocking capability due to parasitic body diode. The battery will also boost the 3.7V rail if it falls down more than about 0.65V below battery voltage (about 4.2 for a Li-Io cell). Clever, but a bit borderline design i must say.

 

[Hicham M]

Hi,

with voltage drop it's easy: the 3.7V supply is derived from 5V supply by dropping voltage across 2 diodes. Typical silicon diode such as those used in the circuit have drop of about 0.65V, so you get 3.7V. But if you look at the I-V characteristic in the datasheet of LL4007 you will see that at current of 2A the drop os almost 1.1V, so altogether you will get 2.2V of drop.

With mosfet the things are a bit tricky. The gate is typically at 5V and the source at 3.7 so Vgs is positive and mosfet is off. When the 5V rail falls below 3.7V the mosfet will start turning on it will connect 3.7V rail to battery effectively powering the 3.7V rail from it. Obviously, the mosfet will conduct from drain to source which is rather "non conventional" direction for a p-mos. It provides a low resistance path through the channel, but doesn't have any blocking capability due to parasitic body diode. The battery will also boost the 3.7V rail if it falls down more than about 0.65V below battery voltage (about 4.2 for a Li-Io cell). Clever, but a bit borderline design i must say.

Thank you for the clarification, it was really helpful.

I checked the datasheed for the LL4007G and TMBYV10-40FILM (D4 and D5) and at 2A I found that the voltage drop are respectively 1.1V and 0.7V, gives a total drop of 1.8V and the 3.7V rail will fall down to 3.2V, is it possible to know from the datasheets if the voltage drop in D4 and D5 can reach 2.2V ?