I would not even try, as many of the elements have
significant C-V swings and you'd have to do a number of
closed-form calculations @ bias-points to "put a box
around it".
But that's from an "actually doing it" perspective, not a
"finish the assignment" one.
I don't like the Cslow idea, it will add phase lag which is
the opposite of what stability wants. Baggage on top of
any internal compensation in the op amp. If you really
want to compensate with shunt-C after the main amp then
maybe you want an uncompensated op amp. But then
Cslow will have to be electrically large (by IC standards)
or you may need to add a series R between amp output
and MC1 gate. But you def don't want to keep stacking
poles, rather than making one that's right.