Analog switch vs MOSFET

[mrinalmani]

Hello!
I need to charge a 1nF capacitor upto a reference voltage of around 1 to 2 volts.
A MOSFET doesn't serve the purpose because of the threshold issue.
Can an analog switch solve the problem? The capacitor must charge right upto the reference voltage without any drop due to threshold or other issues.
Please see the attachment for the connection diagram.
Thanks.

 

[crutschow]

Yes, a CMOS analog switch will do what you want as long as Vdd power to the switch meets the switch's requirements.
How rapidly do you need to charge the capacitor?

 

[D.A.(Tony)Stewart]

THe unspecified problem I believe is the OPs largest voltage Vdd is Vref or not much more and that 1 to 2V causes problems for precise tolerance of Vgs threshold, e.g. tolerance 1.5V +/-0.5V.
The next is availability. THere are sub 1V Vgs switches, but what tolerance?

What is required is an ultralow threshold switch with a low threshold. In this perhaps a PNP.

If my assumption is correct or Vdd is not much higher than Vref then an ultra low Rce PNP will work with <8mV offset @25'C such as follows;

Otherwise the Op is incorrect and a higher Vdd can easily switch Vref with a logic level N type or P type MOSFET.

 

[mrinalmani]

Yes, a CMOS analog switch will do what you want as long as Vdd power to the switch meets the switch's requirements.
How rapidly do you need to charge the capacitor?

Thanks for the reply!
The capacitor must charge to around 2V in 2 to 3 micro-seconds.
The voltage input can be approximated by a unit-step jump from 0 to 1V and then a 1st order ramp to 2V in 3us.
The voltage accuracy must be around 1%, which means 10 to 20mV error is ok.

To suppress overshoot and oscillations I have placed a series resistance of approx 30 ohms (including internal resistance of switch)
Since this is a first order system, the error to a ramp signal is already around 10mV, therefore I want the switch to produce the least possible error, preferably less than 10mV

- - - Updated - - -

SunnySkyguy:
PNP will need a negative signal. I don't have one.

 

[D.A.(Tony)Stewart]

Thanks for the reply!
The capacitor must charge to around 2V in 2 to 3 micro-seconds.
The voltage input can be approximated by a unit-step jump from 0 to 1V and then a 1st order ramp to 2V in 3us.
The voltage accuracy must be around 1%, which means 10 to 20mV error is ok.

To suppress overshoot and oscillations I have placed a series resistance of approx 30 ohms (including internal resistance of switch)
Since this is a first order system, the error to a ramp signal is already around 10mV, therefore I want the switch to produce the least possible error, preferably less than 10mV

- - - Updated - - -

SunnySkyguy:
PNP will need a negative signal. I don't have one.

For 99% linear charge on a capacitor a 5T minimum charge time is required. ( 60% or 1T)
, thus for 5T=1us or T=200ns= 1nF*R thus R=200 Ohms max.

No negative voltage required for PNP just sink base current to ground and collector pulls up to Emitter for Vce <10mV on low Rce device after current Ic, decays <30mA.

What is Vsource 2V? and Vref 1~2V?
What is the Vref source impedance? variable voltage? Is this supposed to be a variable low side switch from 2V to Vref or a high side switch to a low impedance Vref in 3us?

 

[ohenri100]

Hello,
You can use evey nmos as a switch or tranmission gate as a switch. The tranmission gate has the enable signal for control.

 

[crutschow]

What supply voltage do you have?