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Analog signal delay of 120ms

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bimbla

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I want to delay a single channel audio signal(20Hz to 20K Hz) by upto 120ms. To reduce the complexity, I have shortlisted a

Cirrus Logic Audio CODEC CS4224. I need to choose a microcontroller and a suitable audio DSP. I want to use PIC

Microcontroller. I was wondering if I could use large memory to delay the signal and completely eliminate the DSP block.
I need suggestions to go about achieving this.
Delay of 120ms (B.W of 20K) is all I want.

All suggestions welcome.

bimbla.
 

flatulent

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memory

The memory method should work. All you need is a read address pointer and a write address pointer that both increment and are different by the right number of addresses to make your delay.
 

bimbla

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120ms delay

Could you suggest me the type of memory I should use?

Thanks for your reply.

bimbla.
 

flatulent

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not an expert

I am not enough of an expert in the details of digital design to know what memories are available at this time. Some other site member should give you this information. One thing is that the memory is not required to be very fast.
 

mr_ghz

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Hi bimbla

To achive a bandwidth of 20kHz you need a sampling frequency above 40kHz, I suggest using 48kHz. Your codec is a stereo 24Bit one, so for every sample you need 2*24Bit = 6Bytes of memory. For a delay of 120ms this gives 5760 samples, each 6Bytes, so you need 34kByte Memory. The accestime is about 1.5us (read and write), this is not a problem for the memory but for your PIC it would be too fast.
So I suggest you using a faster microcontroller (8 or 16 Bit) and a static memory with 64k*8 or 64k*16 Bit in size. Another possibility is to use a CPLD or FPGA (e.g. Alter Flex)

Bye
 

bimbla

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120ms delay

Thanks for the maths work.
If I have to replace a UC from the scheme, Can I use an FPGA and implement the memory in the same. Can a single chip soln. be possible?

Kindly advice.

bimbla.
 

mr_ghz

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Hi bimbla

64kByte memory is a lot for inside a FPGA (it exist, but it's expensive). So I think you have to use an external SRAM. A one chip solution is difficult, because you also have your codec... But with three chips it should be possible: FPGA, codec and a SRAM.

Bye
 

bimbla

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120ms delay

I will therefore be using Xilinx XC9532, the Cirrus Logig codec.

Any suggestions in choosing specific make of SRAM based on easy availablity?

thanks for all the help.

bimbla.
 

bimbla

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PTC (www.ptc.com.tw) has some IC's under Echo/ Delay category which seem to do just the

thing. Does any one have any experience with these?

bimbla.
 

artem

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If you prefer serial digital coding use ADPCM method ,
let say to use SRAM , but sampling freq will be much high .
 

penrico

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I don't believe you can address a 48K or 64Kbytes or more inside a XC9536 there is not enoght flip-flops to do it!!!!!.

If you use a 32Kbytes memory, you will need: 15 Flip-Flops to Input Address (address of data cames from AD to memory), + 15 Flip-Flops to Output Address (address of data from memory to output), and many flip flops else to control, I recomend use a large CPLD (XC9572 or more).

Using a PIC, is a good choice, with 20 Mhz cristal, it must work.
 

wayhow

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I think one AD+XC9572+fifo(64K byte) can do this well, do not need PIC
 

mr_ghz

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Hi all

Using a PIC, even with 20MHz clock, won't give enough performance. Think on the protocol used for reading/writing the codec. The XC9536 CPLD is surely too small for this application. The XC9572 can be large enough.

Bye
 

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