I have the reference input:10MHz .6V pk-pk.PLL is locked at 1.4GHz.
It has PFD,Loop Filter & VCO. How will I ensure if it's Digital or Analog?I do not have any information about the topology of blocks.
Plz send papers descriping operation of PLL as High Frequency(1.4GHz) Local Oscillator.
You should be aware of that there is not only a distinction between "analog" and "digital" PLL`s. In most cases, modern PLL applications are "semi-analog" resp. "semi-digital" insofar as some components are analog (loop filter with an analog control voltage output) and some units produce digital signals (PFD with charge pump).
A "full digital" PLL incorporates only logical devices including a number-controlled oscillator and some sort of a digital filter.
You should be aware of that there is not only a distinction between "analog" and "digital" PLL`s. In most cases, modern PLL applications are "semi-analog" resp. "semi-digital" insofar as some components are analog (loop filter with an analog control voltage output) and some units produce digital signals (PFD with charge pump).
A "full digital" PLL incorporates only logical devices including a number-controlled oscillator and some sort of a digital filter.
How will I understand from a simple datasheet which component is analog & which is digital?How do I know if PFD has the charge pump?The datasheet doesn't say anything.
I have a 10Mhz input to a on chip PLL Reference Oscillator. The PLL is given to be locked at 1.4Ghz. What's the output from on chip PLL Reference Oscillator? What's it's significance?
How will I understand from a simple datasheet which component is analog & which is digital?How do I know if PFD has the charge pump?The datasheet doesn't say anything.
I am going through Datasheet of GP2015(RF Front End) of Zarlink.
Why the LO frequencies are choosen this way?Do you think if double conversion was used by generating higher LO frequency, the architecture would have been much better?
Because your first and original question was related to the PLL part of the chip:
As can be seen from the figures of the IC data sheet, the loop filter to be connected externally is a typical passive second order filter configuration which is used at the charge pump output. This assumes that an current integrating capacitor is located inside the chip.
Thus the PLL incorporates a classical charge pump PFD producing an analog control voltage for the VCO.
Using the parts values as indicated in Fig. 4 of the data sheet, there is a zero at app. Fz=2 kHz and a pole frequency at app. Fp=25 kHz.