Analog layout sheks list (top and call level)

So many people in that forum are interrested in tanner or calibre ...
So many companies have shek|ist ...
Let' share them ...
Let's try to do the impossible exhaustive one, post your cheks ...

Analog layout shek|ist
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Top level sheks :
-----------------
Die size versus package
Bonding diagram pin order
Bonding diagram XY coordinates
All DRC/LVS log files stored in a database
All LVS warning explained and documented
Device part name and version in top metal
No active devices in chip corners
If multi-supplies, ESD protection between VSS supplies
Shielding on critical nets : Nwell and top metal
Supplies star routed

Cell level sheks :
------------------
Supply width
Transistor matching and dummies:
- same shape
- same orientation
- cross coupling
- same surrounding
Resistors matching and dummies:
- same shape
- same orientation
- cross coupling
- same surrounding
Check parasitic capacitances for high speed and switched-cap designs
Antenna diodes on input gates
Nice shield for critical cells
Test probe opening on critical nodes

OkGuy ?

Hi Okayguy,

How do you normally do the Bonding diagram XY coordinates? Do you manually measure the center of each pad coordinates? What is supplies star routed?

PP

Look this :
**broken link removed**

PolygonPusher,draw a star from your power pads and you avoid voltage drop due to the current that supply noisy blocks. But, the bond wire inductor and its noise is still there !

Anyone can PM to me some design schecklist ?

OkGuy.