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Analog Layout Questions...

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rameshiloveu

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Questions :

1. Why do we have STI ? specially in lower technology nodes compared to larger nodes ?
2. Why do we need to meet minimum density rules ? What's the issue if density is low at some areas causing a groove during cmp ? Why is the planarity needed ?
3. What is requirement to put dummy's at top and bottom more stringent at lower technology node compared to larger nodes?
4. When we draw a transistor , why do we have a large active rectangle and poly over it rather than source/drain active regions and poly ?
5. How do we route current and how do we route voltage?

Please Help !!!

Thanks and Regards,
 

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