Analog Comparator Phase Margin Issue

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jalinmes

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Hi All,

I am now designing a dc to ac buck converter . There is a comparator in a voltage loop. I am now getting a severe phase delay when I tried to sense the output voltage and do the subtraction with Vref.

Is it possible that the delay is mainly contributed by the comparator?

Thank you very much,
 

If you are talking about hysteretic PWM mode, then the main delay is caused by the LC output circuit.
The comparator won't make a big contribution normally.
 

I think so too. Now my Vref is above 600KHz and I need to do the subtraction between Vref and Vsen ( which is proportional to Vout)

Is there a way to avoid these two to be too out of phase with each other? This is what stops me from pushing the frequency higher.

Thank you,
 

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