Using internal or external Vref ?
If internal then Vdd is one issue to deal with. Take your scope, put it on infinite
persistence, and look at your supply rail. If your Vdd is 5V then 1 LSB =~ 5 mV, so
if Vdd rail noise, pk-pk, is 200 mV thats 40 lsb's of random error measuring full
scale.
You are adhering to ADC clock specifications.....?
If you supply a "clean" Vin of say 1/2 scale you still get noise out in readings ?
That indicates supply and layout issues. If no noise then when looking at actual
signal you have coupling issues into ADC, like C coupling adjacent pin logic
activity, long lead/traces picking up environmental stuff like fluorescent lights....
You could do a simple test code, all other HW shutoff, to either dismiss this as
an issue or work on it as a problem.....
Had a chance to look at Vin pin with a spectrum analyzer (lightly coupled) to
get clues of noise origin .....
It also helps in some chips to shut off other HW when doing a conversion, like
PWMs and other noise generating processes....
Keep in mind since you are single ended input any CM noise is a poroblem for you, that
includes coupled noise, noise due to ground bounce, etc....
I see this note in datasheet -
The maximum recommended impedance for analog sources is 10 kΩ
Regards, Dana.