Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 entity Device is generic ( s : integer); port ( out_sig : out std_logic; in_sig : in std_logic_vector(s-1 downto 0); mode : in std_logic; clk : in std_logic ); end Device; architecture Program of Device is component DFF is -- DFF is a synchronious D-trigger port ( Q : out std_logic; D : in std_logic; Clk : in std_logic ); end component; signal d, q, in_value : std_logic_vector(s-1 downto 0):= (others => '0'); signal i : integer := 0; begin in_value <= in_sig; out_sig <= q(0); g1: for i in 0 to s-1 generate begin DFF_inst : DFF port map ( CKJ => clk, D => d(i), Q => q(i) ); end generate g1; process (mode, in_sig, q) begin if mode= '0' then d<= in_sig; else d <= '0'& q(s-1 downto 1); end if; end process; end Program
"d" is not unary. "d" is std_logic_vector(s-1 downto 0) declared in line 17.I'm not expert in HDL, but it seems a little strange in line 32, the assignment of a vector 'in_sig' to a unary signal 'd'. In addition, CKJ wasn't declared anywhere.
I'm not expert in HDL, but it seems a little strange in line 32, the assignment of a vector 'in_sig' to a unary signal 'd'. In addition, CKJ wasn't declared anywhere.
VHDL isn't programming it is actually digital logic design, but it seems you want to go into Analog design, so push back and don't take digital design classes, tell your uni you want to take only Analog/RF classes.
ding, ding, ding! seems you have a friend that knows something about digital design, might want to talk to them next time you have a problem that needs a quick answer.
VHDL isn't programming it is actually digital logic design, but it seems you want to go into Analog design, so push back and don't take digital design classes, tell your uni you want to take only Analog/RF classes.It's not that i'm lazy or something but it's just that i'm not really into programming as much as my uni wants me to
ding, ding, ding! seems you have a friend that knows something about digital design, might want to talk to them next time you have a problem that needs a quick answer.Thank you all for your answers, i do really appreciate your help! Especially big thanks goes to CataM for giving me a good explanation. My friend has done some research with the code and found out that the code might be a parallel to serial converter, may that be right? It works kinda like shift to right register, am i right?
I have explained how it works. Yes, it loads some parallel data with mode='0', stores it, and with mode='1' takes it out like a shift to right register adding '0' to its MSB.My friend has done some research with the code and found out that the code might be a parallel to serial converter, may that be right? It works kinda like shift to right register, am i right?
I agree with ads-ee. I did not read that at the very beginning. I thought it was a practicing problem.Teacher gave as a test to do at home and i have struggles with one of the test.
Haha i guess i will talk to him about that lol.
Talking about classes, i cant actually choose. They want us to learn logical devices..If i wanted to learn more about analog design i would have to choose a different uni but its too late since im a 4th year student already haha.
so if each question was worth 2 points: 5*2 = 10, therefore assuming you did all the other questions correctly getting this extra question results in a change of marks from 80% to 100%. You do realize that makes it unfair for those that actually spent time on working out the questions themselves. Those students may have gotten only 1 point on that question and ended up with a 90% mark, whereas you got the answer from a professional engineer that does this for a living (so is going to know the answer at a glance).Well, that was only one question, but it was worth 2 points. The other 4 test questions were more simple and i did them.
so if each question was worth 2 points: 5*2 = 10, therefore assuming you did all the other questions correctly getting this extra question results in a change of marks from 80% to 100%. You do realize that makes it unfair for those that actually spent time on working out the questions themselves. Those students may have gotten only 1 point on that question and ended up with a 90% mark, whereas you got the answer from a professional engineer that does this for a living (so is going to know the answer at a glance).
That is why I don't answer homework or test questions, but instead try to get the student to figure the problem out or look at it in a different way.
Oh, my then my math was wrong it's actually...The test question i showed you on there was worth 2points, we had 4 more questions: 0.5p,0.5p,0.5p and 1,5p.
My only issue with such a statement is that getting a good/passing marks on something you actually don't know is basically a lie. I've interviewed enough liars in my time. Put them on the spot (they claim to be an expert in VHDL/Verilog) and it turns out they can't even code a counter correctly and had top marks in their class. Seems to me that their degree isn't worth what their marks claim, this is why I could care less what phenomenal marks a recent grad has, but instead interview with the intent to see if they can actually think and analyze a problem.Our class group consists of ~15 students and we all work as a team so most of them had similar answers to each others.
I actually dont really about the grade as long as i pass..Since its not something i enjoy doing (vhdl).
If you don't like it and aren't good at it, then IMO you should probably not have a passing grade (you probably should have dropped the class once you realized you didn't like it). I suppose wherever you are going to school doesn't allow you to specialize in a area you actually like and are good at, which I consider a disservice to the students and probably a push to cater to "donations" from industry for a certain type of engineer (like all engineers are supposed to be round pegs even when they are a square peg being force into that round hole :rollI actually dont really about the grade as long as i pass..Since its not something i enjoy doing (vhdl).
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