I have a simple code and I want to simulate it in cadence but I'd rather not use Verilog-A. I appreciate your thoughts and comments if anything crosses your mind!
Code:
if ((V(WL)-Vth)>0) VDC=2;
else VDC = 0;
Also, during the simulation, if one time "VDC=2" happens I don't want it to change "VDC" anymore.
Use a comparator to compare V(WL)(+) against Vth(-) . If V(WL)>Vth, the comparator output is high. That turns on a switch to pass 2V. If not, turns off the switch and ground the switch output.
Use a comparator to compare V(WL)(+) against Vth(-) . If V(WL)>Vth, the comparator output is high. That turns on a switch to pass 2V. If not, turns off the switch and ground the switch output.
My bad, I forgot to add this part. I think you got my point now.
While (Clock) being
if ((V(WL)-Vth)>0) VDC=2;
else VDC = 0;
end
Assuming VDC=2, I want it to happen only one time. For example, a capacitor can store the value. The thing is that I don't have ideal elements and I have to use actual transistors and capacitors.
That works but a comparator needs at least 4 elements and a latch 8 elements. It doesn't work for me as it needs at least 10 elements. I was thinking of sth with less than 10 elements.