AMS Verification without using SystemVerilog

[imbichie]

Hi All,

Is there anyone know a standard Verification flow like UVM/OVM in AMS Design verification?

Here i am using the AMS designs either in Verilog-AMS or in VHDL-AMS, but for the verification i must not use the SystemVerilog (otherwise i can adopt the UVM).
So is there any formal flow for the AMS Verification?

Thanks in Advance

 

[TrickyDicky]

Whats the reason for not using SV?

if this is the case, you will have to probably do a lot of the verification flow yourself. There is a very good random number generation package with the OS_VVM (https://osvvm.org/) that you can base your verification modules around.

 

[imbichie]

Whats the reason for not using SV?

Hi TrickyDicky,

Thanks for your reply, actually my aim is to Verify the AMS design which is in either Verilog-AMS or VHDL-AMS. But if i am using the UVM concepts here its difficult to understand by the AMS Designer, because they also need to use the same verification environment for Bug fixing. So from the AMS designer's side learning a new verification environment like UVM and a language like SystemVerilog is very difficult; that is why i am searching for a new verification environment for the AMS

 

[rwender]

You might want to look at ViaDesigner. This software combines: VHDL, Verilog, SPICE and VHDL-AMS into a unified design and simulation environment. You can download ViaDesigner at **broken link removed**.