Amplifier design question about P-MOSFETs and N-MOSFETs

[ahmad_abdulghany]

Amplifier design

Hello
I have the following Question:
I want to bias the points X, Y, and Z (shown).. knowing that Y and Z are the gates of P-MOSFETs while X is the gate of an N-MOSFET, can I mirror to the P-MOSFET via an N-MOSFET? or I must do it with similar type (i.e. P-MOSFET also)? The same thing is applied to the N-MOSFETs?
If answer to this question is YOU CAN'T MAKE BIAS TO P-MOSFET EXCEPT WIHT ANOTHER P-MOSFET, then can Vx=Vy ?? or what?? or it has a method to solve??
I hope anyone helps..
Thanks.

 

[bageduke]

Re: Amplifier design

I think you can call figure 1 as current mirror, but figure 2 is not current mirror anymore, since it just uses resistor dividers to generate bias voltages

 

[flushrat]

Re: Amplifier design

I think it's better to generate x y z by separate branches, because sometimes Vx>Vy.

 

[gszczesz]

Amplifier design

In my opinion Figure 1 is easier to understand.
Lets assume that the drop across the current source is significant and positive. This means the reference PMOS cascode has a smaller drop across itself then the load PMOS cascode that is connected to Vdd. If there isn't some clever sizing and current scaling between the reference branch and the load branch, we can assume that the load branch does not have enough current to deliver the required saturation level, and as such the cascode PMOS mirror is simply acting as a resistor (in linear region).

We therefore have a NMOS diff amp with an NMOS common-gate cascode feeding into a PMOS resistor. This circuit is certainly valid and there is no issue between X and Y sharing the same voltage.

Figure 2 is another story. Ideally, that PMOS voltage should be referenced to Vcc. Instead, we are providing it a voltage referenced to GND, 4 diode drops from GND to be more specific. Therefore, if Vcc varies, the reference voltage would not but the voltage acros the top PMOS would. We are therefore not giving a stable operating point for the PMOS. That top PMOS could be anywhere from tottaly turned off, in the linear region or saturated and all that is defined by Vcc and not the bias cuircuit. This is therefore a bad bias configuration.

Now do note that Figure 1 could also be considered referenced from "GND" just 3 diode drops. However, Figure 1 does guarantee the top PMOS will always be turned on since we are giving it the PMOS voltage + whatever is left across the current source. In figure 2 we are giving it only what is across the current source, which is tottaly undefined.


Greg