Yes, the tools assume the second code.
The same is true in VHDL.
we acts as an enable for the assignment statement so the assignment only occurs if that "enable" is high otherwise there is no assignment made, i.e. the value is not updated.
In the case of a RAM there is no feedback around a FF. The RAM cell at the address never gets written in the first place. It's more than likely if you add a explicit ram <= ram; assignment you'll end up not synthesizing RAM but will instead end up with a FF based memory.