Regarding dual edge triggered flip-flops, I mean to remember that it's available in some CPLDs. Interestingly the IEEE standard for synthesizable VHDL (IEEE 1076.6) provides a syntax describing dual edge triggered FFs. But of course it's meaningless for all regular FPGAs that don't support the feature. And as far as I understand, Verilog IEEE Std 1364.1 isn't prepared to describe similar hardware, the document assumes there's only a single posedge or negedge event representing the clock.