May 19, 2016 #1 S Shashidhara Newbie level 1 Joined May 19, 2016 Messages 1 Helped 0 Reputation 0 Reaction score 0 Trophy points 1 Activity points 9 Hi, We have always@(*) flexibility to add all the signals in the sensitivity list. do we have anything equivalent in VHDL something like process(*) Thanks in advance Shashidhara
Hi, We have always@(*) flexibility to add all the signals in the sensitivity list. do we have anything equivalent in VHDL something like process(*) Thanks in advance Shashidhara
May 19, 2016 #2 ads-ee Super Moderator Staff member Joined Sep 10, 2013 Messages 7,944 Helped 1,822 Reputation 3,654 Reaction score 1,808 Trophy points 1,393 Location USA Activity points 60,207 Process(all)
May 20, 2016 #3 T TrickyDicky Advanced Member level 7 Joined Jun 7, 2010 Messages 7,110 Helped 2,081 Reputation 4,181 Reaction score 2,048 Trophy points 1,393 Activity points 39,769 process(all) is the answer with VHDL 2008 There is no equivalent in VHDL '93
May 20, 2016 #4 V vGoodtimes Advanced Member level 4 Joined Feb 16, 2015 Messages 1,089 Helped 307 Reputation 614 Reaction score 303 Trophy points 83 Activity points 8,730 also no equivalent in verilog in 1993, 23 years ago. complain to tool vendors if you want vhdl-2008 support in 2016.
also no equivalent in verilog in 1993, 23 years ago. complain to tool vendors if you want vhdl-2008 support in 2016.