alu design problem please help

i am trying to make an alu but i am in initial stage. please help me ; i wrote the alupack.vhd file which gives me no error during compilation. code is here
library ieee;
use ieee.std_logic_1164.all;
package alu_types is
subtype bits_32 is std_logic_vector(31 downto 0);
---type bit_array is array (integer range <>) of bits_32;
subtype bits_8 is bit_vector(1 downto 0);
constant lda: bits_8 :="00"; ---these are the instructions
constant ldr: bits_8 :="01";
constant add: bits_8 :="10";
constant sub: bits_8 :="11";
end package alu_types;
second file which i have made is alufunc.vhd but this gives me an error while compiling which is lda,ldr,add,sub are not directly accessible and ** Error: C:\Modeltech_pe_edu_10.0a\examples\alufunc.vhd(21): Constant "lda" is type work.alu_types.bits_8; expecting type ieee.std_logic_1164.STD_ULOGIC. similarly for other instructions as well... please help me.... thanks in advance.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.alu_types.all;entity alu_func is
port (op1,op2 : in bits_32;
en: in std_logic;
rslt : out bits_32);
end entity alu_func;

architecture behav of alu_func is

begin
alu rocess
variable ac,reg :bits_32;
---variable op: bits_8;
begin

case en is
when lda =>
ac:=op1 after 1 ns;
when ldr =>
reg:=op2 after 1 ns;
when add =>
ac:=ac+reg after 1 ns;
when sub =>
ac:=ac-reg after 1 ns;
end case;
rslt<=ac after 1 ns;
end process alu;
end architecture behav;

Why are you using both bit_vectors and std_logic_vectors?

i am using std_logic_vectors sorry it is not bit_vector

you are doing a case statement on the enable bit, which is a single bit. It cannot have cases that are 2 bits.
Are you sure you meant to put "en" in the case statement?>

trickydicky please clear me... i put it to just enable the case and then lda or add must have an op code to choose statement

but enable is only a single bit. You cant compare a 1 bit signal to 2 bit constants.