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| module top (
clock ,
reset ,
numa ,
numb ,
opcode ,
result
);
input clock,reset,opcode;
input numa,numb;
output result;
wire clock,reset,opcode;
//parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100 ;
generate
always @ (posedge clock)
if(opcode == 2'b00)
u_mult multi(result,numa,numb);
else if(opcode == 2'b01)
u_mult u_booths_mul(result,ready,numb,numa,start,clock);
else if (opcode == 2'b02')
u_mult u_divide(quotient,remainder,ready,numa,numb,start,clock);
else
endgenerate
endmodule
module u_mult(product,multiplier,multiplicand);
input [15:0] multiplier, multiplicand;
output product;
reg [31:0] product;
integer i;
always @( multiplier or multiplicand )
begin
product = 0;
for (i=0; i<16; i=i+1)
if ( multiplier[i] == 1'b1 )
product = product + ( multiplicand << i );
end
endmodule
module u_booths_mul(product,ready,multiplicand,multiplier,start,clk);
input [15:0] multiplicand, multiplier;
input start, clk;
output product;
output ready;
reg [31:0] product;
reg [4:0] bit;
wire ready = !bit;
initial bit = 0;
wire [17:0] multiplicand_X_1 = {2'b0,multiplicand};
wire [17:0] multiplicand_X_2 = {1'b0,multiplicand,1'b0};
wire [17:0] multiplicand_X_3 = multiplicand_X_2 + multiplicand_X_1;
always @( posedge clk )
if ( ready && start ) begin
bit = 8;
product = { 16'd0, multiplier };
end else if ( bit ) begin:A
reg [17:0] pp; // Partial Product
reg [1:0] mb; // Multiplier Bits
mb = product[1:0];
case ( mb )
2'd0: pp = {2'b0, product[31:16] };
2'd1: pp = {2'b0, product[31:16] } + multiplicand_X_1;
2'd2: pp = {2'b0, product[31:16] } + multiplicand_X_2;
2'd3: pp = {2'b0, product[31:16] } + multiplicand_X_3;
endcase
product = { pp, product[15:2] };
bit = bit - 1;
end
endmodule
module u_divide(quotient,remainder,ready,dividend,divider,start,clk);
input [15:0] dividend,divider;
input start, clk;
output [15:0] quotient,remainder;
output ready;
reg [15:0] quotient;
reg [31:0] dividend_copy, divider_copy, diff;
wire [15:0] remainder = dividend_copy[15:0];
reg [4:0] bit;
wire ready = !bit;
initial bit = 0;
always @( posedge clk )
if ( ready && start ) begin
bit = 16;
quotient = 0;
dividend_copy = {16'd0,dividend};
divider_copy = {1'b0,divider,15'd0};
end else begin
diff = dividend_copy - divider_copy;
quotient = { quotient[14:0], ~diff[31] };
divider_copy = { 1'b0, divider_copy[31:1] };
if ( !diff[31] ) dividend_copy = diff;
bit = bit - 1;
end
endmodule |