PCB Designers
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Altium Summer 09 : Handling BUS in Hierarchical Mode
Hi to all,
I am working on a Project and stcuked because of a problem in handling BUS in Hierarchical Mode.
Rather referencing the complex design, I am placing an example to make you understand my problem.
The Top sheet consists of 3 Connectors J1, J2, J3.
J1 (on left) produce a bus of X[0..15] and enters the same bus after spliting into X[0..7] AND X[8..15] to sheet symbols (DSTBT1 and DSTBT2).
These sheet symbols refers to Sheet 2, which recieves 8 nets as BUS and place them on 2 switches SW1 and SW2 (buffers in actual circuit) .
The SW1 out 8 signals as DATA_OUT[0..7] , and SW2 out 8 signals as ADD_OUT[0..7]
Now back to sheet1 (top/parent sheet)
Each Sheet symbol has sheet entries DATA_OUT[0..7] and ADD_OUT[0..7], now I want connector J2 & J3 to connect their Buses as shown in Sheet 1.
J2 has a bus D[0..15], which is sliced and connected to both Sheet symbols. same is with J3.
I thought, that it will connect 16bit D[0..15] bus with the two 8 bit sheet entries of DATA_OUT[0..7] of 2 sheet symbols and it will connect 16bit A[0..15] bus with the two 8 bit sheet entries of ADD_OUT[0..7] of 2 sheet symbols.
But, on compilaion it is producing 2 ERROR:
1) Duplicate Net Names Bus Slice D[0..15]
2) Duplicate Net Names Bus Slice A[0..15]
What should be the proper method to connect these buses, what am I doing wrong here ?
I am looking for a very comprehensive response from Altium Users.
Best Regards,
Maqbool
Hi to all,
I am working on a Project and stcuked because of a problem in handling BUS in Hierarchical Mode.
Rather referencing the complex design, I am placing an example to make you understand my problem.
The Top sheet consists of 3 Connectors J1, J2, J3.
J1 (on left) produce a bus of X[0..15] and enters the same bus after spliting into X[0..7] AND X[8..15] to sheet symbols (DSTBT1 and DSTBT2).
These sheet symbols refers to Sheet 2, which recieves 8 nets as BUS and place them on 2 switches SW1 and SW2 (buffers in actual circuit) .
The SW1 out 8 signals as DATA_OUT[0..7] , and SW2 out 8 signals as ADD_OUT[0..7]
Now back to sheet1 (top/parent sheet)
Each Sheet symbol has sheet entries DATA_OUT[0..7] and ADD_OUT[0..7], now I want connector J2 & J3 to connect their Buses as shown in Sheet 1.
J2 has a bus D[0..15], which is sliced and connected to both Sheet symbols. same is with J3.
I thought, that it will connect 16bit D[0..15] bus with the two 8 bit sheet entries of DATA_OUT[0..7] of 2 sheet symbols and it will connect 16bit A[0..15] bus with the two 8 bit sheet entries of ADD_OUT[0..7] of 2 sheet symbols.
But, on compilaion it is producing 2 ERROR:
1) Duplicate Net Names Bus Slice D[0..15]
2) Duplicate Net Names Bus Slice A[0..15]
What should be the proper method to connect these buses, what am I doing wrong here ?
I am looking for a very comprehensive response from Altium Users.
Best Regards,
Maqbool
Last edited: