ALTIUM: Multi Part Component and PCB / Schematic link ?

[alexglvr]

Hello,

In a the schlib of my altium project, I defined a Xilinx FPGA as a multi-part component (PARTA : Bank0, PARTB : Bank1, PARTC : Bank2, PARTD : Bank3, PARTE : Supply).

I decided to use hierachical schematic design with one sub schematic per FPGA Part.

Then, an upper lever schematic implements all the FPGA sub schematic in order to define the complete FPGA circuit.

A top level schematic implements 5 of this circuit to define a 5 FPGA Board.

It gives this Schematic hierarchy:

TOP.sch
....|_ FPGA.sch x 5
...........|_ Bank0.sch
...........|_ Bank1.sch
...........|_ Bank2.sch
...........|_ Bank3.sch
...........|_ Supply.sch

The problem is when I do a "Design\Update PCB document TOP.pcbdoc" my generated PCB does not have 5 FPGA but 25 (one per Subcircuit)...

I do not find how to solve that... Could you help me please?

Thank you,

Alex

 

[Anonymous_Ricky]

There is a tutorial in Altium for "Multi sheet and Multi Channel Design" please go through it.
This will help you.

Ricky

 

[alexglvr]

I read it, but do not manage to find how to deal with my case...

I spent the morning trying things, and i now have more informations...

Here is my schematic Hierarchy :

TOP.sch
..|_FPGA.sch
........|_Bank0.sch
........|_Bank1.sch
........|_Bank2.sch
........|_Bank3.sch
........|_Supply.sch

NB : the FPGA component has been definied as a multipart component (XC6), and each part of the component is used in one of the FPGA.sch sub-circuit (Bank0.sch uses XC6_1A,, Bank1.sch uses XC6_1B, etc...)

1. If my TOP design (TOP.sch) implements 1 FPGA structure (one sheet symbol pointing to FPGA.sch), it works well. My generated PCB has a single FPGA.

2. If my TOP design uses several FPGA structures, then the sub-circuit seems not to be recognised and i have a footprint per FPGA sub-circuit on the generated PCB

And yet, the sheet symbols used on the TOP schematic to instanciate FPGA.sch do not have the same designator, neither the same Unique ID...

It looks like if altium was not keeping the hierachy after the FPGA.sch level. It then deals several FPGA components part, but do not manage to merge them correctly to create the full component...

Some help please?

Alex