alternate of for loop

[QMA]

Dear all
please tell me is there any alternate for 'for' loop in verilog. i am using xilinx. please explain me how?

 

[pbernardi]

You are facing your problem in a SW way, which is wrong.

The correct approach is: what HW do you want to have? do you want several components in parallel? multiple accesses? a counter? a memory?

Several different kind of HW can be achieved by a "for" concept.

 

[QMA]

actually i am designing a code whose one component is memory. i have to replace all for loops with any other alternative. it will utilize less resources and improve efficiency. please help me and correct me if my concepts are wrong.

 

[dpaul]

It completely depends on what you want to implement.
e.g.- For the for loop, you might have in mind to do some operation on a variable after a certain limit is reached.
You can also do this with else-if.
What's the difficulty?

"please explain me how?" - there are numerous example out there for Verilog and is a very very elementary thing!

 

[QMA]

It completely depends on what you want to implement.
e.g.- For the for loop, you might have in mind to do some operation on a variable after a certain limit is reached.
You can also do this with else-if.
What's the difficulty?

"please explain me how?" - there are numerous example out there for Verilog and is a very very elementary thing!

Dear
for example, I have a 16x16 RAM. there are certain bits which are 1's. I have to calculate number of 1's in some particular address. let suppose address RAM[10] has the value 0001000000100000. if want to design a counter which will calculate the number of 1's in some given row. Also if I change the index of RAM to some runtime value. like i give the address through test bench each time i run the code and want to have results as output.

 

[dpaul]

The following EDA board post might help you. All you need to change are the signal/port sizes.
https://www.edaboard.com/threads/111774/

As a side note- You should ask the Q as you did in #5 and not as in #1 in order to receive faster and proper answers.

 

[QMA]

please examine code given for a selected row of ram which has number of 1's equal to 2. i have the code using for loop. now i want to change it with if/else. but it is not giving me the results. please help me.

always @ (*)
	begin
	    bits_s_row = 16'b0;
		 pop_count = 4'b0;
		 B_addr = input_data[3:0];
		 R_addr = input_data[7:4];
		 bits_s_row[0:15] = ram[R_addr];
		 out = bits_s_row[B_addr];
		 i = 4'b0;
		 if(i<=B_addr)
		 begin
		  if(bits_s_row[i]==1)
		  pop_count = pop_count + 1'b1;
		  else
		  pop_count = pop_count;
		  i = i+1'b1;
		  end
		 else
         out = out;   
	 end
endmodule

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dpaul
u have given me very helpful link. thanks.
how can i implement it using Look up table? OR how can i use case statements. which one would be better for high speed, low resources etc.

 

[ads-ee]

Verilog is not a software programming language so don't write it like software. Any good Verilog book will tell you what is synthesizable or not.

Counters require flip-flops to store the current count, which is the updated on the next clock cycle. Using for loops or if statements doesn't matter until you understand the hardware you are designing. In HDL for loops are used create replicated logic not to create temporal delays in logic.

 

[QMA]

thanks dear. Please guide me through an example. how can i implement a counter using flip flops? How can I count number of 1's in a given register or to a particular location of register.

 

[FvM]

If you "count" ones in 16 bit wide word with a for loop, you generate combinational logic which can give the result in one clock cycle, but only at moderate speeds. Counting the bits one-by-one takes 16 clock cycles. Pipelined logic or lokk-up tables give probably the best speed versus resources trade-off.

The design snippet in post #7 isn't counting bits. There's no for loop or other iteration scheme used.

 

[ads-ee]

how can i implement it using Look up table? OR how can i use case statements. which one would be better for high speed, low resources etc.

To know which one is better in terms of resources comes from knowing exactly what a hardware synthesis tool will generate for any given HDL representation. The results may vary depending on the synthesis tool and the optimizations it does.

Fastest speed (clock frequency) always means writing code that is highly pipelined. Low resource usage usually means less pipelining and a correspondingly low clock frequency. Both high speed and low resources usually means a completely different architecture for the design, i.e. bit-serial implementations, time-divsion multiplexed logic, etc. (trades latency for efficiency).

 

[QMA]

If you "count" ones in 16 bit wide word with a for loop, you generate combinational logic which can give the result in one clock cycle, but only at moderate speeds. Counting the bits one-by-one takes 16 clock cycles. Pipelined logic or lokk-up tables give probably the best speed versus resources trade-off.

The design snippet in post #7 isn't counting bits. There's no for loop or other iteration scheme used.

actually i tried it using if else. but it was not giving me the results.

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verilog is new for me. i am not very much used to it. i am getting the idea which ads-ee has given above. please tell me how can i use pipelining for designing a counter.

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shall i use case statement? but it works like MUX. i mean it will give me output comparing value of input just once. how can it become a counter?

 

[ads-ee]

A basic counter is written like this:

---

Code Verilog - [expand]
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reg [7:0] count = 0;
always @ (posedge clk) count <= count + 1;

---

The temporal reference is the clock clk and it counts up every clock edge. This synthesizes to a circuit like this:

 

[QMA]

i have found a solution from another thread. it is
"i would prefer to use combinational logic (I just love it)...

let's use a 2 input OR gate, connect one of the input pin to GND, another to the one bit of the 32 bits. if it's a '1' in the bit, it will output a 1... after you have done this with all the 32 bits, you can use an adder to add up all the 32 bits output from the OR gates "

it will at least require an upper limit to control the counter for gate first to last. am i right

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A basic counter is written like this:

---

Code Verilog - [expand]
1
2
reg [7:0] count = 0;
always @ (posedge clk) count <= count + 1;

---

The temporal reference is the clock clk and it counts up every clock edge. This synthesizes to a circuit like this:
View attachment 120414

thanks u so much dear. it is making concept. please tell me how can i limitize this counter(count up to some given index). moreover if i want to count for a number of registers stored in memory. i mean in SW it can be accomplished using nested loops. in HW how can i use the idea using above example. One more thing I am getting from the above fig that the count will take 8 clocks to end up. i think it is not pipelining.

 

[dpaul]

I was of the opinion that there were several examples in the link I had provided. Just implement the one of your choice, the one which uses less resources. As ads-ee has mentioned, read a good Verilog book, write down the code and simulate it. If you have problems there the forum members can help you.

 

[ads-ee]

Well this code:

---

Code Verilog - [expand]
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module counter #(
    parameter MAXCNT = 12
) (
    input clk,
    input rst,
    input ena,
    output reg [3:0] cnt
);
 
    always @ (posedge clk) begin
        if (rst) begin
            cnt <= 0;
        end else if (ena && cnt < MAXCNT) begin
            cnt <= cnt +1;
        end
    end
 
endmodule

---

produces the following schematic for a kintex 7 part.


there are 4 flip-flops in the design and it counts each clock cycle while reset is low, ena is high, and the count value is between 0-11. Once the count reaches 12 it stops counting. The waveform looks like this:


Now if you want to see what other counters or code looks like, then download either the Altera or Xilinx web versions of their tools and see that the synthesis schematics look like by selecting the technology view of the design.

 

[vGoodtimes]

https://cdstahl.org/?p=747

This blog post shows multiple versions of bit-counting, including the SW-based approach. There is some code listed as well, so you should be able to try each style out and see if newer synthesis tools have different results. All designs on that page represent the same logic and there is the potential more modern synthesis tools will do just fine with for-loops in this application.