It completely depends on what you want to implement.
e.g.- For the for loop, you might have in mind to do some operation on a variable after a certain limit is reached.
You can also do this with else-if.
What's the difficulty?
"please explain me how?" - there are numerous example out there for Verilog and is a very very elementary thing!
always @ (*) begin bits_s_row = 16'b0; pop_count = 4'b0; B_addr = input_data[3:0]; R_addr = input_data[7:4]; bits_s_row[0:15] = ram[R_addr]; out = bits_s_row[B_addr]; i = 4'b0; if(i<=B_addr) begin if(bits_s_row[i]==1) pop_count = pop_count + 1'b1; else pop_count = pop_count; i = i+1'b1; end else out = out; end endmodule
how can i implement it using Look up table? OR how can i use case statements. which one would be better for high speed, low resources etc.
If you "count" ones in 16 bit wide word with a for loop, you generate combinational logic which can give the result in one clock cycle, but only at moderate speeds. Counting the bits one-by-one takes 16 clock cycles. Pipelined logic or lokk-up tables give probably the best speed versus resources trade-off.
The design snippet in post #7 isn't counting bits. There's no for loop or other iteration scheme used.
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 module counter #( parameter MAXCNT = 12 ) ( input clk, input rst, input ena, output reg [3:0] cnt ); always @ (posedge clk) begin if (rst) begin cnt <= 0; end else if (ena && cnt < MAXCNT) begin cnt <= cnt +1; end end endmodule