@ltera VS Xilinx
Hi,
Am not able to reply in PM am replying here..
"what is the acutal diffrence between the code that one may write for simulation and code for synthesis ?"
There is no difference between synthesis and simulation code for RTL, whatever u r coding should be synthesizable. In test bench(TB) u can include the not synthesizable code like wait statement. Bcoz TB is not used for synthesize.
The codes are not different for different tools..
The code has to follow the verilog or VHDL standard.. Usually if u written any non-synthesizable code Modelsim simulator will show warnings. If it is wrt TB file u can safely ignore the warning. If it is wrt RTL then u must remove the warnings.
Tools used in Altera for synthesis is quartus II..
U can download this in altera website.. for web edition no license is required.
Latest quarus version is 9.0
Hope this may helps u..
If u hav further queries / or this info is not clear please send me message.
Best Regards,
Shanmugavel D