Re: Help Plz new to verilog
Hard to read your code with no indents. But as a general comment you should not divide clocks in logic. FPGAs and CPLDs have special clock lines and when you couple them to logic you lose the advantages of having low skew clock lines.
What you really want to do is generate a clock enable signal. I don't do much Altera any more but Xilinx expects your flop to look like this:
always @(posedge clock)
if (sync_reset) q<=0; else
if (clock_enable) q<=~q;
The order is significant. So if you write in this order you will get a "natural" flip flop (check the Altera docs, but I'd bet it is the same).
So then the key is you want to generate a clock enable pulse at the right time for your desired frequency. So I'd have one counter that generates the clock enable at whatever ratio 25.7E6 is to 19.2E3.
So in broad terms:
wire bitclocken;
reg [31:0] clockdiv; /* you may need more or fewer bits */
assign bitclocken=(clockdiv==0);
always @(posedge clk)
if (reset) clockdiv<=32'bXXXXXXX; // use your timing constant
else if (clockdiv==32'b0) clockdiv<=32'bXXXXXXX; // same constnat
else clockdiv<=clockdiv-1;
always @(posedge clk)
if (bitclocken) begin
// the stuff in here will only happen at the "slow" clock rate set by XXXXXX
end
Hope that helps.
Al W.
PS
Verilog stuff at **broken link removed**