The timing diagrams are only simplified for clarity, I think. In a ususal synchronous design, all input signals to the RAM block would be sourced from registers also clocked on the rising edge, changing it's output a short time after the risidng edge. Of course, they work perfectly, as they do in other places of the design.
For FPGA generated signals to the RAM, the timing analyzer is watching about setup and hold times. In case of external signals, you may want to create a larger timing margin. In this case, changing of signals on falling edge may be reasonable, of course.