std_match
Advanced Member level 4
In the Altera example timing diagrams, they always change address/data on the falling clock edge, and the RAM does it's job on the rising edge. I would prefer to clock everything on the rising edge. I can't find any discussion about this. Of course, the address/data hold times will be worse, but I can't find any warning against that method.
All suggestions are welcome!
All suggestions are welcome!