I am running 32-bit counter in Quartus. I have used the PIO to read the data but i am facing the problem, data is not in sequence in which PIO receiving the data slowly from FPGA. So, i think FIFO is best to store and read the data in NIOS.
I am new to the altera, please anyone share the FIFO example design or else guide me in FIFO design.
What if the Nios is always slower (or faster) at reading the data compared to you supplying it with new data?
Simply using a FIFO won't suffice in such a case.
You'll also have to monitor the FIFOs flags...
If the purpose of your project is simply to see things working - you don't have to design your own FIFO. Just generate one via the IP catalog wizard.
I can tell you only what this should be done in Xilinx's software/chip.
I would suggest to create AXI FIFO and connect it to the CPU (hard or soft CPU). Then export hardware to the SDK, where you should find .h, .c and test.c files in BSP (Board Support Package).
Then the app in CPU depends on what you want to do.
If you want to read FIFO content in CPU, then check for empty flag and read from FIFO all the time until empty='1'. The FPGA design is complementary for write.
If you want to write to FIFO in CPU, then check for full flag and write to FIFO all the time until full='1'. The FPGA design is complementary for read.
I can tell you only what this should be done in Xilinx's software/chip.
I would suggest to create AXI FIFO and connect it to the CPU (hard or soft CPU). Then export hardware to the SDK, where you should find .h, .c and test.c files in BSP (Board Support Package).
Then the app in CPU depends on what you want to do.
If you want to read FIFO content in CPU, then check for empty flag and read from FIFO all the time until empty='1'. The FPGA design is complementary for write.
If you want to write to FIFO in CPU, then check for full flag and write to FIFO all the time until full='1'. The FPGA design is complementary for read.
I am new to the Altera Quartus software tool.So Please anyone guide me to accomplish my task.
Design Process involves:
1. Need to compile 8-bit, or 32-bit or 64-bit counter in Quartus
2. Interconnect the counter module with NIOS using SOPC
3. Want to see counter result in NIOS console
1. Need to compile 8-bit, or 32-bit or 64-bit counter in Quartus
2. Interconnect the counter module with NIOS using SOPC
3. Want to see counter result in NIOS console
For above design, i Have followed the below step but in NIOS data is not printing in proper sequence (randomly printing). I dont know why ?
VERILOG code
Code:
odule counter
(
input clk, enable, rst_n,
output reg[7:0] count
);
always @ (posedge clk or negedge rst_n)
begin
if (~rst_n)
count <= 0;
else if (enable == 1'b1)
count <= count + 1;
end
endmodule