I know that Altera IP's (for example - a FIFO) can be added to a project by declaring the altera_mf library and instantiating the appropriate core in HDL (with the required parameters/generics set).
Are there any cases when HDL instantiation is impossible and I MUST use the QIP file?
the .QIP file is only needed if you generate a core. There is no requirement to ever use it for any core, but when your core consists of 100s of source files, then adding just the .QIP file is a good idea.
You'll need it for anything not in the Altera_MF library - for example the PCIE core, ethernet core, SRIO core etc.
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Also if you use anything generated in QSYS, I recommend using the generated .QIP