Mr.Cool
Advanced Member level 2
new to CPLDs... but trying to learn
using MAX7000S CPLD 44 pin type.
i have a healthy clock, oscillating at 10MHz, 50% duty, between 0 and 4.75V. it is applied to the global CLOCK pin 37.
i have INPUT pin for CLOCK assigned to pin 37, and some I/O with simple primitive logic. circuit seems to work with output correct. but then i make some changes using flip-flops and i start to doubt that the clock is actually working (the first simple version must have been working on asynchronous basis only?)
using only primitives and block diagrams.. how do i check if the clock is working inside the chip? so i just connected the CLOCK pin through a "wire" block and connected to an OUTPUT pin and assigned it to spare pin. i expect to see the clock here after download to device.
but i see only the CLOCK pin's initial state (which is defined as VCC). if i change CLOCK pin to initial state GND, then this is what i see on the output pin.
what am i doing wrong?
Mr.Cool
using MAX7000S CPLD 44 pin type.
i have a healthy clock, oscillating at 10MHz, 50% duty, between 0 and 4.75V. it is applied to the global CLOCK pin 37.
i have INPUT pin for CLOCK assigned to pin 37, and some I/O with simple primitive logic. circuit seems to work with output correct. but then i make some changes using flip-flops and i start to doubt that the clock is actually working (the first simple version must have been working on asynchronous basis only?)
using only primitives and block diagrams.. how do i check if the clock is working inside the chip? so i just connected the CLOCK pin through a "wire" block and connected to an OUTPUT pin and assigned it to spare pin. i expect to see the clock here after download to device.
but i see only the CLOCK pin's initial state (which is defined as VCC). if i change CLOCK pin to initial state GND, then this is what i see on the output pin.
what am i doing wrong?
Mr.Cool