altera MAX7000S CPLD - clock not working?

[Mr.Cool]

new to CPLDs... but trying to learn

using MAX7000S CPLD 44 pin type.

i have a healthy clock, oscillating at 10MHz, 50% duty, between 0 and 4.75V. it is applied to the global CLOCK pin 37.

i have INPUT pin for CLOCK assigned to pin 37, and some I/O with simple primitive logic. circuit seems to work with output correct. but then i make some changes using flip-flops and i start to doubt that the clock is actually working (the first simple version must have been working on asynchronous basis only?)

using only primitives and block diagrams.. how do i check if the clock is working inside the chip? so i just connected the CLOCK pin through a "wire" block and connected to an OUTPUT pin and assigned it to spare pin. i expect to see the clock here after download to device.

but i see only the CLOCK pin's initial state (which is defined as VCC). if i change CLOCK pin to initial state GND, then this is what i see on the output pin.

what am i doing wrong?

Mr.Cool

 

[FvM]

In my opinion, MAX7000 should be able to connect a clock input to an output pin. So you should actually see the clock input.
But to be sure, you should check the RTL netlist and also the physical mapping of your synthesis software. It can reveal,
if the intended connection actually exists. What's the involved synthesis tool?

Generally, you can also connect a clock divider (D-FF with inverted feedback) to the clock input for test.

 

[Mr.Cool]

i am using Quartus II, free download from manufacturer.

i tried other circuits like an input that i could pull high or low externally.. and ran this through a DFF and then through to an OUTPUT pin. but at this output pin i do not see the toggling input. more reason to believe that the clock is not working.

however, other output signals (that do not involve clock signals) toggle according to their input.. so the CPLD is generally working. it is just the internal clock that does not seem to be recognized and used. clock is stuck in its initial state.

is there some option/setting that i am supposed to engage to inform the CPLD that i want to use the clock rather than just combinatorial logic ?

Mr.Cool

 

[farhada]

How about just connecting the input to an output and see if the input pin works, then you can test it one step further to see if it toggles

For Altera CPLDs, you can test the IOs differently, using it as a simple output does not use the CLK buffer part of the IO block, but at least give you a hint if the pin is healthy or not.

 

[FvM]

I don't understand the problem. Either the clock input is damaged or you're doing someting odd.

 

[Mr.Cool]

you are a wise man... i was doing something odd.

when i compiled the program and then selected "programmer" the file that programmed into the machine had the same file name, but did not come from the programm i just compiled! no wonder i didn't notice the problem... sheesh.. coincidence that it had same file name.

so i smacked myself in the head.. selected the correct file .. programmed it and everything worked out fine.

thought i was going insane there..

sorry to waste peoples times.. i should be more patient and work through the problems before posting for assistance.

Mr.Cool