Altera logic programmer card (PLP6)

Similar threads

• H

  Altera DE2-115 SDRAM byte enables

  • Started by hexaeder
  • Mar 18, 2024
  • Replies: 4

  PLD, SPLD, GAL, CPLD, FPGA Design
• J

  [SOLVED] Trying to write SPI SD Card reader in verilog, getting weird data from CMD17

  • Started by JustusJohnston
  • Jun 22, 2023
  • Replies: 7

  PLD, SPLD, GAL, CPLD, FPGA Design
• Z

  [SOLVED] Vitis vadd example crashes on Alveo U280 card at line 30 of host.cpp

  • Started by zzzhhh
  • Jun 4, 2023
  • Replies: 0

  PLD, SPLD, GAL, CPLD, FPGA Design
• P

  Implement carrier detection logic in FPGA

  • Started by pulkit.vlsi
  • Dec 26, 2022
  • Replies: 5

  PLD, SPLD, GAL, CPLD, FPGA Design
• O

  Altera DE2 115 GPIO pin

  • Started by Oscar99haha
  • Jul 31, 2022
  • Replies: 1

  PLD, SPLD, GAL, CPLD, FPGA Design