Altera internal error again

[fanwel]

Hi all;

I have previous problem that still cannot solve. I have try to use the new version of quartus2 but the internal error still occur.
I also have try to delete the db and db_increment directory but still not work. The compilation is work for the first time, before I turn on the Generate Value Change Dump File Script option (Assignments>Settings). Below is my code and the internal error:
----------------------------------------------------------------------------------------
library ieee;
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;

package my_data_types is
type sfixed_array_t is array (0 to 3) of sfixed (9 downto -8);
end my_data_types;

library ieee;
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
use work.my_data_types.all;

entity reg_one is
port (clk: in bit;
Ra: in sfixed_array_t;
out_Ra: out sfixed_array_t);
end reg_one;

architecture reg_one of reg_one is
begin
process(clk)
begin
if (clk'event and clk='1') then
for i in 0 to 3 loop
out_Ra(i) <= Ra(i) after 10ns;
end loop;
end if;
end process;
end reg_one;
----------------------------------------------------------------------------------
Internal Error: Sub-system: WSC, File: /quartus/neto/wsc/wsc_port.cpp, Line: 514
m_port_info.num_of_dimensions() == 1
Stack Trace:
0x251D8 : WSC_PORT::bus_member_index + 0x88 (NETO_WSC)

End-trace

Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition
------------------------------------------------------------------------------------
Can anyone helps me please..really need helps. Thanks

 

[TrickyDicky]

have you tried quartus version 11?

did you know that the "after" keyword will be ignored in quartus? Why would you want after anyway, when it is a clocked process?

 

[fanwel]

Yes, I already send a request to the altera MySupport.
I want to generate the output after 10ns..thanks for reply

 

[TrickyDicky]

delays like that are not possible on real hardware.

 

[fanwel]

How can I make the delays 10ns on the real hardware? Some books write like out <= in after 10ns for have a delay..
thanks for reply

 

[FvM]

I guess, no VHDL book talks about using delay statements for hardware synthesis. Basically, you need synchronous designs and a respective fast clock. You'll face however the problem, that synchronous designs can change a signal state only at a clock edge, not at an exact delay relative to an input signal.