If you need a slower clock, here is a simple clock divider algorithm, that divides the clock by 2N.
Where :
N = F(crystal) / 2* F(desired)
-- file "clk_div.vhd"
-- a generic clock divider, divides by 2*N
-- adapted from "VHDLL Primer" by J. Bhasker, p. 295
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity clk_div is
generic(N: positive:= 2);
port
(fast_clk, reset: in std_logic;
slow_clk: buffer std_logic
);
end clk_div;
architecture behavioural of clk_div is
begin
process(reset, fast_clk)
variable count: natural;
begin
if reset = '1' then
count := 0;
slow_clk <= '0';
elsif rising_edge(fast_clk) then
count := count + 1;
if count = N then
slow_clk <= not slow_clk;
count := 0;
end if;
end if;
end process;
end behavioural;