altera global clock division

[bbgil]

I'm trying to use the global clock setting of altera Max 7000s but it is too fast for my design. How do i slow it down? do i need to put a clock division program in my architecture? If so, can anybody help me? I'm modelling a project based on a 2 Hz clock system. Thanks in advance.

 

[Iouri]

@ltera global clock division

what is an input frequency? and what is you desired frequency?

 

[bbgil]

my input frequency is the global clock setting of Max 7000s (24.5 MHz). i tried using decoder to slow it down but i'm having problem on the vhdl architecture part coz its requires longer programming. my desired frequency is 2 - 5 Hz. thanks for any input.

 

[benzwishc]

maybe you can use clock setting to get your clock tree in quartus,at first you set an individual clock as a base clock, and then you generate the derived clock from the base clock,good luck

 

[Iouri]

@ltera global clock division

What was wrong to impliment simple counter?

 

[xihushui]

@ltera global clock division

i think u can use exterior clock generated by youself.i suggest y don't use dividor to u design.division maybe generate lots of question.

 

[sp]

@ltera global clock division

this is clock division i always use to obtain slower clk..

If you need a slower clock, here is a simple clock divider algorithm, that divides the clock by 2N.

Where :

N = F(crystal) / 2* F(desired)

 

-- file "clk_div.vhd"

-- a generic clock divider, divides by 2*N

-- adapted from "VHDLL Primer" by J. Bhasker, p. 295

------------------------------------------------------------------------------------------

  
library ieee; 
use ieee.std_logic_1164.all; 
  
entity clk_div is 
generic(N: positive:= 2); 
port 
(fast_clk, reset: in std_logic; 
slow_clk: buffer std_logic 
); 
end clk_div; 
  
architecture behavioural of clk_div is 
begin 
process(reset, fast_clk) 
variable count: natural; 
begin 
if reset = '1' then 
count := 0; 
slow_clk <= '0'; 
elsif rising_edge(fast_clk) then 
count := count + 1; 
if count = N then 
slow_clk <= not slow_clk; 
count := 0; 
end if; 
end if; 
end process; 
end behavioural;

 

[sree205]

@ltera global clock division

preferably, use macros provided in quartus itself. it ll save a lot of resources.