harezmi
Newbie level 1
Hi ı have a problem about this verilog code ı dont understand what does it mean ? Can someone explain this code thanks...
reg [0:0] pix_flop, R_B_line, new_img, new_line;
input pclk, vsync, hsync;
always @(posedge hsync) begin
R_B_line <= ~R_B_line;
if(~new_img) R_B_line <= 0;
end
reg [0:0] pix_flop, R_B_line, new_img, new_line;
input pclk, vsync, hsync;
always @(posedge hsync) begin
R_B_line <= ~R_B_line;
if(~new_img) R_B_line <= 0;
end