Altera FPGA RAM example

[shaiko]

A single port VHDL RAM example from Altera:

process(clk)
begin
if(rising_edge(clk)) then
if(we = '1') then
ram(addr) <= data;
end if;		
[COLOR="#FF0000"]addr_reg <= addr[/COLOR]; -- Register the address for reading
end if;	
end process;

q <= ram(addr_reg);

my question:
why use "addr_reg" for reading? why not simply use:

q <= ram(addr);

 

[TrickyDicky]

because that would be an asynchronous read. If you look at the technology, it has an optional read_address register embedded in the memory part. This code uses that register, and will help improve the timings.

- - - Updated - - -

IIRC, in XILINX BRAMs you MUST use a registered version of the read address.

 

[shaiko]

Yet it uses an unregistered version of the write address??

 

[TrickyDicky]

You can use the registered version if you want.. But what it's actually doing is loading the data into a pre-memory data register, and it will be registering the address as well (in the technology).

Check the technology map schematic.