altera fir compiler channel manage

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franticEB

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hi,
i'm using fir compiler to implement a fir filter with 4 channel in one wire and decimation factor=16.
Now i have difficulties in managing the signal SOP, EOP, SINK_VALID and SOURCE_READY in order to make the filter work.
The sample rate of the input data is 200KHz and the system clock is 50MHz.
How could pass the parallel data that comes @200khz sample rate to my filter?
How could manage the signals SOP, EOP, SINK_VALID and SOURCE_READY?
I expect that the outputs is about 12.5KHz...
Could you help me?
 

Where does the data come from? does it also use the 50MHz clock? if it does then there must be some way of marking the data valid otherwise you would have a lot of invalid data.
 

the data come from ad converter...then the sampled data are multipied by sine and cosine...in other words i'm talking about iq demodulator with two branches...
 

ok - you still have something that controls the data flow? a valid signal? or a fifo? this will be easy to connect to your sink_valid and source_ready.
 

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