Hi,
I'm using the "dcfifo" mega function, from Altera Quartus V 5.0, to design a 16550 UART in VHDL.
The FIFO works fine.
I use it in "Show-ahead synchronous FIFO mode”.
- The first time the power is on, the FIFO is empty, the output q[11...0] sends a "0" when the uControler reads it.
Right.
- Then it receives true data.
-When the FIFO has been read for 16 times (depth of the FIFO), the data shown in q[11...0] is not "0" (the FIFO is empty).
Usually it shows the last value received or random values.
It is not very important, because the FIFO marks empty, then the value in q[11...0] is not valid.
I've tried a UART from Philips and National and the value read is always “0” (if the FIFO is empty).
Anyone has encounterd this problem or something similar?
Thank's in advance.