For example, I want to implement an 8-bit counter and see the result 1, 2, ..., 255.
I'm presently using Quartus 9 on Windows 7 to maintain Cyclone and Cyclone II designs. Not sure if it runs on Windows 10, but not impossible.
Any suggestion for that? If the capability is limited to one push button and 3 LEDs, then why using a 60K logic elements and a 114 pin chip?!So that means very very limited board!
I was thinking about sending/receiving data through JTAG or AS ports. For example, sending a 32 bit data and receiving its checksum. Is that possible?
Any suggestion for that? If the capability is limited to one push button and 3 LEDs, then why using a 60K logic elements and a 114 pin chip?!
OK. That was good. I restarted the windows 10 in the test mode as explained in that page and then installed the blaster driver. The driver files are located in quartus\driver folder. Now it works.Try some of the stuff here before uninstalling and reinstalling the huge installations of QuartusII.
https://www.howtogeek.com/228689/how-to-make-old-programs-work-on-windows-10/
I know that I have to put some seven segments or LCD on the bread board and connect them to the IO pins. However, I was thinking on how to send/receive data to/from computer. For example, setting A and B as two floating point numbers in the VHDL code and then get the multiplication and display on the monitor. Is that possible with this board? If you know any guide, please let me know.Have you seen the rows of parallel pins surrounding the FPGA? If, yes have you consulted the board development guide as to how can you use them?
In my opinion serial interface would be the simplest (keeping the tx and rx pins separate).However, I was thinking on how to send/receive data to/from computer. For example, setting A and B as two floating point numbers in the VHDL code and then get the multiplication and display on the monitor. Is that possible with this board? If you know any guide, please let me know.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity uart is
generic
(
clk_freq : integer := 50000000; -- hertz
baudrate : integer := 460800 -- bits/s
);
port
(
rxd : in std_logic;
rx_data : out std_logic_vector(7 downto 0);
rx_busy : out std_logic;
txd : out std_logic;
tx_data : in std_logic_vector(7 downto 0);
tx_start : in std_logic;
tx_busy : out std_logic;
clk : in std_logic
);
end uart;
architecture rtl of uart is
signal txstart : std_logic := '0';
signal txsr : std_logic_vector (9 downto 0) := (others => '1'); -- start bit, 8 data bits,
signal txbitcnt : integer range 0 to 10 := 10;
signal txcnt : integer range 0 to (clk_freq / baudrate) - 1;
signal rxd_sr : std_logic_vector(3 downto 0) := (others => '1'); -- edge detection and synchronization
signal rxsr : std_logic_vector(7 downto 0) := (others => '0'); -- 8 data bits
signal rxbitcnt : integer range 0 to 9 := 9;
signal rxcnt : integer range 0 to (clk_freq / baudrate) - 1;
begin
-- send
p_send : process
begin
wait until rising_edge(clk);
txstart <= tx_start;
if (tx_start = '1' and txstart = '0') then -- rising edge, start
txcnt <= 0; -- init counter
txbitcnt <= 0;
txsr <= '1' & tx_data & '0'; -- stop bit, 8 data bits, start bit, start rightmost
else
if txcnt < (clk_freq / baudrate) - 1 then
txcnt <= txcnt + 1;
else -- output next bit
if txbitcnt < 10 then
txcnt <= 0;
txbitcnt <= txbitcnt + 1;
txsr <= '1' & txsr(txsr'left downto 1);
end if;
end if;
end if;
end process p_send;
txd <= txsr(0); -- LSB first
tx_busy <= '1' when tx_start = '1' or txbitcnt < 10 else '0';
-- receive
p_receive : process begin
wait until rising_edge(clk);
rxd_sr <= rxd_sr(rxd_sr'left - 1 downto 0) & rxd;
if rxbitcnt < 9 then -- receiving
if rxcnt < (clk_freq / baudrate) - 1 then
rxcnt <= rxcnt + 1;
else
rxcnt <= 0;
rxbitcnt <= rxbitcnt + 1;
rxsr <= rxd_sr(rxd_sr'left - 1) & rxsr(rxsr'left downto 1); -- shift right, LSB first
end if;
else -- wait for start bit
if rxd_sr(3 downto 2) = "10" then -- falling edge of start bit
rxcnt <= ((clk_freq / baudrate) - 1) / 2; -- wait for half of bit time
rxbitcnt <= 0;
end if;
end if;
end process p_receive;
rx_data <= rxsr;
rx_busy <= '1' when rxbitcnt < 9 else '0';
end architecture rtl;
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