Altera Avalon Streaming Interface template?

[konradb]

I want to use an Altera FIR mega function. To connect to it I have to use the Avalon Streaming Interface.

I want to connect an ADC, filter the signal and store the result in SDRAM.

Has anyone got a VHDL template or example of the streaming interfcae I can use to get me started.

I use Altium and I have an ADC VHDL component connected to my own homebrew filter VHDL component to my own DMA VHDL component that connects to wishbone. The wishbone and avalon MM interface seem very similar, but the streaming interface is just a little more complicated.

As an aside, would it be recomended for me to use the SOPC to build a subsystem rather than manually writning code?
This must be a very common task, but I can't find any examples of a VHDL component that reads an ADC and streams Avalon.


Regards
Konrad

 

[konradb]

This is something I've started,
does this look ok?

library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.Std_Logic_arith.all;
use IEEE.Std_Logic_signed.all;

entity AD7492_CTRL is port
   (
        CLK     : in    std_logic;
        RST     : in    std_logic;
        ast_SOURCE_SOP   : out    std_logic;
        ast_SOURCE_EOP   : out    std_logic;
        ast_SOURCE_READY : in    std_logic;
        ast_SOURCE_VALID : out    std_logic;
        ast_SOURCE_DATA  : out    std_logic_vector(11 downto 0);
        ast_SOURCE_ERROR : out    std_logic_vector(1 downto 0);   -- error, not implemented
        xD        : in    std_logic_vector(11 downto 0);
        nCSI      : out   std_logic;
        nCSQ      : out   std_logic;
        nSTART    : out   std_logic;
        BUSY      : in    std_logic;
        M_SAM_I   : in    std_logic             -- Master Sample in
   );
end AD7492_CTRL;
--------------------------------------------------------------------------------

--------------------------------------------------------------------------------
architecture FSM of AD7492_CTRL is

-- Signal Declarations
signal I_sample: std_logic_vector(15 downto 0);
signal Q_sample: std_logic_vector(15 downto 0);

-- states
type    typeState is (  READY_state,
            START_state,
            BUSY_state,
            READ_I_state,
            DESELECT_I_OP_state,
            SELECT_Q_OP_state,
            READ_Q_state,
            RESULT_I_state,
            RESULT_Q_state,
            EOP_state,
            FINISHED_state);
            
signal  State : typeState;
signal  Next_State : typeState;


begin

    FSM: process
    begin
    wait until CLK'event and CLK='1';

        case State is

            when READY_state =>  -- standby
                nSTART <= '1';
                ast_SOURCE_SOP <= '0';
                ast_SOURCE_EOP <= '0';
                ast_SOURCE_VALID <= '0';
                if M_SAM_I = '1' then
                    Next_State <= START_state;
                end if;

            when START_state => -- start conversion
                nStart <= '0';
                Next_State <= BUSY_state;

            when BUSY_state =>  -- converting
                if BUSY = '0' then
                    Next_State <= READ_I_state;
                end if;

            when READ_I_state =>  -- conversion finished, copy I data result into buffer 
                I_sample(11 downto 0) <= conv_std_logic_vector(conv_integer(xD - x"7FF"),12);
                Next_State <= DESELECT_I_OP_state;

            when DESELECT_I_OP_state =>  -- deselect I I/P
                nCSI <= '1';
                Next_State <= SELECT_Q_OP_state;

            when SELECT_Q_OP_state =>  -- select Q I/P
                nCSQ <= '0';
                Next_State <= READ_Q_state;

            when READ_Q_state =>  -- copy Q data result into buffer 
                Q_sample(11 downto 0) <= conv_std_logic_vector(conv_integer(xD - x"7FF"),12);
                Next_State <= RESULT_I_state;

            when RESULT_I_state =>    -- copy result into o/p buffer
                ast_SOURCE_DATA(11 downto 0) <= I_sample(11 downto 0);
                ast_SOURCE_VALID <= '1';
                ast_SOURCE_SOP <= '1';
                nCSQ <= '1';     -- deselect Q I/P
                Next_State <= RESULT_I_state;

            when RESULT_Q_state =>    -- copy result into o/p buffer
                ast_SOURCE_DATA(11 downto 0) <= Q_sample(11 downto 0);
                ast_SOURCE_VALID <= '1';
                ast_SOURCE_SOP <= '0';
                ast_SOURCE_EOP <= '1';
                nCSI <= '0';     -- select I I/P
                Next_State <= EOP_state;

            when EOP_state =>
                ast_SOURCE_SOP <= '0';
                ast_SOURCE_VALID <= '0';
                Next_State <= FINISHED_state;

            when FINISHED_state =>    -- wait for falling edge of sample clock
                if M_SAM_I = '0' then
                    Next_State <= READY_state;
                end if;

            when OTHERS =>
                Next_State <= READY_state;

        end case;

    end process;


    clock_reset: process (RST,CLK)
    begin
       if RST = '1' then
          State <= READY_state;
       else
          if (CLK'event and CLK='0') then
             State <= Next_State;
          end if;
       end if;
    end process;

    ast_SOURCE_ERROR <= "00";

end FSM;
--------------------------------------------------------------------------------