Allowed values for generic parameters

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ireon

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Hello I wrote a VHDL code where my entity accepts generic parameters. I added some limitations using RANGE function. Now I should add a limitation on data width, but only some value are allowed, in particular the data width parameter can only be 8, 16, 32, 64. Is there a function to do this?
 

you can use assertions in the code to catch illegal generics. I think all synth tools now stop synthesis on failed inline (outside a process) assertions:

Code VHDL - [expand]
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assert data'length = 8 or data'length = 64
  report "Data width must be 8 or 64"
    severity failure;


If you need data width it to be a any of 2 (and can use VHDL 2008):

Code VHDL - [expand]
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assert xor to_unsigned(data'length, 32) = '1' 
  report "Data Width must be 2^N"
    severity failure;
 

Power of two is also "(((not x) + 1) and (x) = x) and (x > 0)". doesn't "xor to_unsigned(7, 32)" return '1'?

You can also have a package with a selector function to map an enumerated type to an integer in a custom manner.
 

vGoodtimes said:
doesn't "xor to_unsigned(7, 32)" return '1'?
Click to expand...

Yes it does - my mistake.
Might be easier just to have a count_bits function instead:

Code VHDL - [expand]
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function count_bits( u : unsigned; s : std_logic := '1') return integer is
  variable n : natural;
begin
  for i in u'range loop
    if u(i) = s then n := n + 1; 
    end if;
  end loop;
  return n;
end function;
 
assert count_bits( to_unsigned(data'length, 32) ) = 1
  report "Data Width must be 2^N"
    severity failure;
 

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