Allegro - few questions

[kazimi]

Hi,

I've started to learn Allegro (16.3) few days ago. Before I began I looked through the Internet, but I couldn't find any decent tutorial. I was looking for a tutorial, which shows how to create simple board including library creation.
I found something like that:
**broken link removed**

But I am confused a little bit, if it is the right way of doing this... Please have a look at the symbols of resistors... Author of this tutorial doesn't use Design Entry CIS - I thought thats the proper tool for schematic.

In fact - what is the difference between Design Entry HDL and Design Entry CIS?

Can anybody tell me, how to create library using Design Entry CIS? I can create schematic part of the component using CIS (*.olb), footprint using PCB Design (*.dra), but I do not know how to map them...

So once again - does anybody posses any decent tutorial? I would be really, really thankful because it starts me driving crazy

Thanks&Regards,
kazimi

 

[Scottm]

The only thing that is neede to map these two together is in the schematic symbol there is a property called PCB footprint, You put the footprint name into that field of the schematic symbol properties and when you create the netlist from CIS the footprint name will come through to allegro.

 

[kazimi]

So we always leave mapping to Allegro? I mean - Allegro does everything? So there is no tool to do mapping by myself? like in eagle for example?

 

[elec4fun]

When you create a PCB footprint, you assign a number to the pad you have created. So the pin number in your schematic symbol has to
match with the pad number in the footprint.

 

[Scottm]

Crevars is correct also, If you are using CIs for your schematic capture the pin numbers on the footprint must match the pin numbers in the schematic, otherwise you will have a problem when trying to get the netlist into allegro. Another small annoying thing in CIS is if you have multiple pins called the same name (e.g NC) they must be named NC1---? as another error occurs calling up duplicate pin names which for some reason CIS doesn't like. There may be a way around this but i don't know what that is.

 

[soumyabumba]

Can I make a layout in PCB editor directly without drawing any schematic and netlist files?

 

[prastesh]

For my knowledge it is not possible.Layout file only represents schematic and net list files.

 

[miskol]

Can I make a layout in PCB editor directly without drawing any schematic and netlist files?

If i'm not mistaken, you can try to do that using GerbTool.

 

[mira2830]

kazimi: I've sent you a PM.

 

[kazimi]

mira2830 - thanks a lot!!!! I think that is the solution for my problem

 

[miskol]

mira2830 - thanks a lot!!!! I think that is the solution for my problem

mind sharing with the forum as well? TQ.