Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Allegro Design Entry HDL-ERROR(SPCOCD-150)Signal connected to pin has incorrect width

Status
Not open for further replies.

mcggoal

Newbie level 2
Joined
Aug 16, 2009
Messages
2
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Location
shenzhen,China
Activity points
1,291
Hi,

I am beginner with cadence, while I draw the power line, I meet a problem:

The DRAM has 9 power pins, while I use 1 power wire to connect them, there is an error:
ERROR(SPCOCD-150): Signal connected to pin has incorrect width.

The pic is in attachment.

DDR3_power.jpg

And I found in the demo, there is an "9=1" mark nearby, which can solve this problem, So I
want to know how to set the "9=1" attribute?

Thanks!
 

Hi,

I am beginner with cadence, while I draw the power line, I meet a problem:

The DRAM has 9 power pins, while I use 1 power wire to connect them, there is an error:
ERROR(SPCOCD-150): Signal connected to pin has incorrect width.

The pic is in attachment.

View attachment 85357

And I found in the demo, there is an "9=1" mark nearby, which can solve this problem, So I
want to know how to set the "9=1" attribute?

Thanks!

Yes, I have solved! Just add component "syn1ton" tap is OK!
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top