u didnt specify your clock freq. i think your skew is ok.As far as slack is concerned, it is desirable to have a small positive slack but try to avoid negative slack.
in case of hold violation, the hold time depends on the fastest path( the path which takes least time to propagate in your logic). so if there is an hold violation means , your signal cannot propagate even the least time path of your logic. this will make your design unfit for use.it directly affects the reliablity of the chip.
if u have any more query in timing issue , kindly read the primetime user guide fundamentals and primetime modelling userguide which i have attached below .
regards
navien