algorithm needed, pleae help (vhdl)!!!

[dark_plan]

Hello!

I need an algorithm for the following scenario:

Let's say I have an input called "start" that goes high for a very short period of time then goes low again. Say I have an output called "b" that goes high for one second as soon as "start" is detected to be high then goes low again.

Pretty easy to explain the scenario but I really can't think of how to code it in vhdl. Still, I tried my luck and came up with the following code:

-----------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;


entity delay is
port(b: out std_logic;
clock, start: in std_logic);
end delay;

architecture archi of delay is
constant counter: natural := 50e6;
signal enableCounter: natural range 0 to counter := 50e6; --- I am using spartan 3e which has a clock speed of 50MHz
signal tick: std_logic := '0';
begin

process (clock, start)
begin
if start = '1' then
if rising_edge(clock) then
tick <= '1';
case tick is
when '1' =>
b <= '1';
if enableCounter = 0 then
tick <= '0';
enableCounter <= counter;
else
enableCounter <= enableCounter - 1;
end if;
when '0' =>
b <= '0';
when others =>
end case;
end if;
end if;
end process;
end archi;
-----------------------------

However, I know just by looking at the code that it's wrong as the line 'if start = '1' then' only gets evaluated for a very short time. Anyone who could perhaps improve the code or help me come up with a better algorithm?
Thanks in advance!

 

[ombadei]

not sure if this will work.. slightly pseudo version..not done vhdl for quite some time.. if i am not wrong.. the below can be done combinationally.. pardon me if it doesnt work for u..

process(start)
begin
if rising_edge(start) then
enableCounter <= 1; //enable 1second counter
else
if one_sec_up == '1' then
enableCounter <= 0;
b <= '0';
elsif enableCounter == 1 then
b <= '1';
end if;
end if;
end process;