lcell what is
It's me again,
Check under 'Functional Descriptions' of the 'ACEX 1K Programmable Logic Device Family Data Sheet' at altera's website. There, you can find information regarding the internal construction of the ACEX.
A LCELL is implemented using one logic element (LE). Refer to figure at page 16, I think what happen is the LCELL's input occupies one of the four LUT's inputs and goes through the Register Bypass wire to the output.
Regarding the CARRY and CASCADE primitives, they are a sort of way to
minimise delays. Imagine the scenario where an XOR function required 8 LEs. With CARRY primitives used, all LEs within an LAB can be chained together. Without the primitive, LEs might be scattered around a few LABs, hence, increasing delays. I hope you can understand what i am trying to say :lol: .
You may also looks for more information at Help file provided by Maxplus or Quartus.
I havent used AHDL b4. You may be right. However, you should be able to obtain a similar level of control using VHDL. Just make sure your code is written at low level.
According to Altera, AHDL manual can be purchased from any Altera distributor.